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Samsung taps Mentor for Closed-Loop DFM
Samsung Electronics’ foundry arm is rolling out an updated version of the Closed-Loop DFM system it first discussed last autumn. The system has been found to deliver yield gains of 10% since...
View ArticleSchematic capture moves to the web with browser engine
At the 53rd DAC, Concept Engineering is introducing a version of its Nlview family of automatic schematic generation products that runs inside a standard web browser. NlviewJS is a schematic engine...
View ArticleMenta launches fourth-generation embedded FPGA core
Programmable-logic specialist Menta SAS has launched its fourth generation of embedded field-programmable gate array (FPGA), expanding support to several additional 28nm and 14nm process technologies....
View ArticleIntento uses graphs to optimize analog blocks
Startup Intento Design has launched an analog-circuit migration and optimization tool based on a technique that is meant to reduce significantly the amount of simulation needed to develop viable...
View ArticleNXP readies single package solution for 77GHz radar
NXP Semiconductors aims to use the kind of radar beam-forming used in military aircraft in the automotive market. It is working on a second flavor of long-range, high-precision 77GHz radar for...
View ArticleAnalyzer merges constraints for multiple timing modes
Ausdia has launched a product intended to reconcile the multiple sets of timing constraints needed for operating and test modes so that a consistent group of constraints can be fed to implementation...
View ArticleMinimize memory moves for greener data centers
Deep pipelines and dynamic memory sharing may provide the key to the development of faster and more efficient server-farm blades as the focus in hardware design moves to augmenting conventional...
View Article2D tools adapt to create smaller monolithic 3DIC designs
Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings. “We call it Shrunk-2D,”...
View ArticleDFT to expand its role for long-term yield
The infrastructure for design for test (DFT) could look quite different in five years time compared to the situation designers have today as chipmakers wrestle with the problems of yield control,...
View ArticleWhat’s the shortest time in the universe?
“It’s the time between putting out an open-source ARM core and getting a letter from an ARM lawyer,” says UC Berkeley professor Krste Asanovic, who leads the RISC-V initiative to develop and promote an...
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